ZYBO Zync-7000 Development Board Work
Getting the LEDs to flash
Welcome to my ZYBO Zynq-7000 tutorial! I'm not too far ahead of you, but there are a few things that I have learned while working with the development board. My objective here is to take you from the very beginning so that you will be able to get your board up and running as soon as possible! While looking online, I've found that there are not many tutorials that deal with the ZYBO board and the Vivado 2014.4 release.
Things you will need
Step 1: Create a project
- Open Vivado 2014.4 and click "Create New Project"
- Click next (not shown) and enter a project name along with its location and click Next (below).
- Choose the correct project type: "RTL Project". Verify that the "Do not specify sources at this time" box is checked.
- Select the correct part. For this tutorial, we are using the Zynq-7000 with the specifications shown below. Click Next. Click Finish(not shown).
- After a few seconds, your project should be created and you will be looking at a window that is similiar to the figure below.
Step 2: Create the block design
- Click on the Create Block Design button within the Flow Navigator.
- A "Create Block Design" window will appear and ask you for the following information. Name your design anything you want, we left it as its default value. Click OK.
- It will create a blank design and then you will notice the below screen.
- Click the "Add IP" link at the top of the design window (the above window boxed in red). A smaller window will appear within the Diagram window. In the search box, type "zynq" and double-click the ZYNQ7 Processing System option.
- You should then see a ZYNQ block within the Diagram window.
- Next, click the Run Block Automation at the top of the Diagram Window Tab. After doing so, you will be presented with the following window. Verify that the processing_system7_0 checkbox is checked and that the Cross Trigger In and Cross Trigger Out drop down selections are both disabled. Click OK
- You will now notice that the DDR and FIXED_IO pins on the ZYNQ processing system block are connected to interface ports of the same name. Your Diagram Window Tab should look like the figure below.
- Right Click anywhere within the Diagram Window Tab and click the Add IP... option from the dropdown menu. A window will appear that is similiar to that which we saw when we first created the ZYNQ processing system block. Within the search window, type AXI_GPIO. There should only be one selection, double click the selection with name AXI_GPIO. After some time, your Diagram Window Tab will look like the below figure.
- Towards the top of the Diagram Window Tab, you will see the Run Connection Automation link. Click that link. After clicking that link, a new Run Connection Automation window will appear. Check the box that is labeled S_AXI and verify that the clock connection is set to "Auto". Click OK.
- After a second or two, more system blocks should appear within your Diagram Window Tab. At the top of the window, click the Run Connection Automation link again. This time, verify that the GPIO checkbox is checked and click OK. After this, there should be three interfaces - DDR, FIXED_IO, and gpio_rtl. Your screen should look like the figure below. Right Click within the Dialog Window Tab and select the Regenerate Layout option from the drop-down menu.
- Double Click on the AXI GPIO block and you will see a window similar to that which is below. Verify that the All Outputs option is selected, the GPIO Width is 4, and that the Default Output Value is 0x0000000F. Click OK.
- Next, Click the Validate Design button and then, if validated successfully, select the Sources Tab. These buttons are highlighted in the figure below.
- Within the Sources Tab, right Click your block design file. For me, this is design_1.bd, which is found within the Design Sources directory. From the dropdown menu, select the option to Create HDL Wrapper. Verify that the radiobutton Let Vivado manage wrapper and auto-update is selected and click OK. This wrapper is where we will begin to edit some of the VHDL code. After creating the wrapper, your sources tab should display the newly created HDL wrapper (design_1_wrapper.vhd for me).
- Before we begin to edit the VHDL wrapper file, we will need to include the XDC file for the ZYBO development board. This file can be found on the digilent website. Once you download this file, in Vivado, click the Add Sources button under the Project Manager, within the Flow Navigator. A window will appear and select the option to Add or create constraints.
- Within the next window, select the Add Files... option and navigate to the directory that you downloaded the ZYBO XDC file to. Check the checkbox labeled Copy constraints files into project. Click Finish.
- Within the Sources Tab, expand the folder labeled Constraints by clicking the +. Within this folder, you should see a file labeled ZYBO_Master.xdc. Open this file. When you open this file, you will notice that all of the lines have been commented out. Leave all of these lines commented except the ones that are shown uncommented below. Save.
- Open the VHDL wrapper file (design_1_wrapper.vhd for me). Make the following changes to lines below and save.
LINE 37 (within design_1_wrapper entity): CHANGE gpio_rtl_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 ) TO led : out STD_LOGIC_VECTOR ( 3 downto 0 ).
LINE 92 (within component instantiation): CHANGE gpio_rtl_tri_o(3 downto 0) => gpio_rtl_tri_o(3 downto 0) TO gpio_rtl_tri_o(3 downto 0) => led(3 downto 0).
- Click the Run Implementation button (shown below), a Missing Synthesis Results window appears. Click OK. If your design hasn't been saved, it will prompt you to save again. If so, click Save. After waiting, a Implementation Completed window will appear. [WARNING: if you get several warnings, it is because the VHDL wrapper file reverted back to its old self. Repeat step 17 and continue.] Within the Implementation Completed window, select the option to Generate Bitstream. Click OK.
- After the bitsteam has been generated, a Bitsteam Generation Completed window will appear. Choose the Open Implemented Design option and click OK.
- Now, its time to export what we created to SDK in order to program the processor. Click File>Export>Export Hardware... An Export Hardware window will appear, select the Include bitstream checkbox option and click OK.
- Let's launch SDK. Go to File>Launch SDK. A Launch SDK window will appear. Simply Click OK.
Step 3: Program the processor with SDK
- SDK should open with a window that is similiar to the figure below.
- Go to File>New>Application Project and you will be presented with a window that is like that which is below. Choose a project name and click Next. In the next window, select Empty Application and click Finish.
- When you click Finish, there should be a C project folder within your Project Explorer. Click the arrow next to the new C project folder and you will not see two more folders: Includes and src.
- Download the following SDK resource file.
- Right click the src folder and choose the option Import... An Import window will appear and you should navigate to General>File System and click Next.
- Click Browse and navigate to the folder that contains the downloaded blink.c source file. Click OK.
- Verify that blink.c is checked in the following screen. Click Finish.
- Plug your ZYBO development board into your computer.
- In SDK, in the menu bar, navigate to Xiling Tools>Program FPGA. You will get to a screen like below. Verify that for Device, Auto Detect is grayed out and that Connection is set to Local. Also, double check to see that the .bit file that was generated in Vivado is in the box labeled Bitstream. Click Program. After completing, the four LEDs above the switches should be illuminated.
- Next, in SDK's menu bar, navigate to Run>Run Configurations. Uncheck the checkboxes Run ps7_init and Run ps7_post_config. Click Apply and then Click Run.
- Tada! Your LEDs should now begin to blink!
<< LED Sequence 0 >>
<< LED Sequence 1 >>
- If there is an error programming the board, turn off/on the ZYBO board and close/reopen SDK (like Step 2.21)